Datasheet

71M6521DE/DH/FE Data Sheet
Rev 3 Page: 59 of 107
Data Flow
The data flow between CE and MPU is shown in Figure 26. In a typical application, the 32-bit compute engine (CE)
sequentially processes the samples from the voltage inputs on pins IA, VA, IB, and VB, performing calculations to
measure active power (Wh), reactive power (VARh), A
2
h, and V
2
h for four-quadrant metering. These measurements
are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU.
Figure 26: MPU/CE Data Flow
CE/MPU Communication
Figure 27 shows the functional relationship between CE and MPU. The CE is controlled by the MPU via shared
registers in the I/O RAM and by registers in the CE DRAM. The CE outputs two interrupt signals to the MPU:
CE_BUSY and XFER_BUSY, which are connected to the MPU interrupt service inputs as external interrupts.
CE_BUSY indicates that the CE is actively processing data. This signal will occur once every multiplexer cycle.
XFER_BUSY indicates that the CE is updating data to the output region of the CE DRAM. This will occur whenever
the CE has finished generating a sum by completing an accumulation interval determined by SUM_CYCLES *
PRE_SAMPS samples. Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
Figure 27: MPU/CE Communication
CE MPU
Pre-
Processor
Post-
Processor
IRQ
Processed
Metering
Data
Pulses
I/O RAM (Configuration RAM)
Samples Data
MPU
CE
PULSES
INTERRUPTS
DISPLAY (me-
mory-mapped
LCD segments)
DIO
EEPROM
(I2C)
SERIAL
(UART0/1)
SAMPLES
VAR (DIO7) W (DIO6)
VARSUM
WSUM
ADC
EXT_PULSE
CE_BUSY
XFER_BUSY
Mux Ctrl.
DATA
APULSEW
APULSER
SAG CONTROL
I/O RAM (CONFIGURATION RAM)