Datasheet

71M6521DE/DH/FE Data Sheet
Rev 3 Page: 55 of 107
Figure 21: Functional Blocks in SLEEP Mode (inactive blocks grayed out)
IA
VA
MUX
XIN
XOUT
VREF
CKADC
CKTEST/
SEG19
CE
32 bit Compute
Engine
MPU
(8051)
CE
CONTROL
OPT_RX/
DIO1
OPT_TX/
DIO2/
WPULSE/
VARPULSE
RESET
VBIAS
V1
EMULATOR
PORT
CE_BUSY
OPTICAL
UART
TX
RX
XFER BUSY
COM0..3
VLC2
LCD DISPLAY
DRIVER
DATA
00-7F
PROG
000-1FF
DATA
0000-FFFF
PROG
0000-7FFF
0000-
7FFF
MPU XRAM
(2KB)
0000-07FF
DIGITAL I/O
CONFIG
2000-20FF
I/O RAM
CE RAM
(0.5KB)
MEMORY SHARE
1000-11FF
RTCLK
RTCLK (32KHz)
MUX_SYNC
CKCE
CKMPU
CK32
CE_E
RTM_E
COMP_STAT
POWER FAULT
LCD_E
LCD_CLK
LCD_MODE
DIO
4.9MHz
<4.9MHz
4.9MHz
GNDD
V3P3A
V3P3D
VBAT
VOLT
REG
2.5V to logic
V2P5
MPU_DIV
SUM_CYCLES
PRE_SAMPS
EQU
CKOUT_E
32KHz
TMUXOUT
MPU_RSTZ
FAULTZ
WAKE
TMUX[4:0]
CONFIGURATION
PARAMETERS
GNDA
VBIAS
December 11, 2006
CROSS
CK_GEN
OSC
(32KHz)
CK32
CKOUT_E
MCK
PLL
VREF
VREF_DIS
DIV
ADC
MUX
CTRL
MUX_DIV
CHOP_E
EQU
STRT
IB
MUX
MUX
CKFIR
4.9MHz
RTM
SEG34/DIO14 ..
SEG37/DIO17
WPULSE
VARPULSE
WPULSE
VARPULSE
TEST
TEST
MODE
LCD_MODE
VLC1
VLC0
LCD_E
<4.9MHz
LCD_NUM
DIO_R
DIO_DIR
LCD_NUM
DIO_PV/PW
MUX_ALT
SEG24/DIO4 ..
SEG31/DIO11
SDCK
SDOUT
SDIN
E_RXTX/SEG38
E_TCLK/SEG33
E_RST/SEG32
FLASH
(16/32KB)
FLSH66ZT
V3P3A
FIR_LEN
FIR
SEG0..18
EEPROM
INTERFACE
DIO_EEX
CK_2X
ECK_DIS
OPT_TXE
V3P3D
LCD_GEN
X4MHZ
PB
RTC
RTC_INC_ SEC
RTC_DEC_SEC
VB
VBIAS
MEMORY
SHARE
SEG32,33
SEG19,38
E_RXTX
E_TCLK
E_RST (Open Drain)
ICE_E
DIO1,2
VREF_CAL
∆Σ ADC
CONVERTER
+
-
VREF
ADC_E
RTM_0..3
CE_LCTN
PLS_MAXWIDTH
PLS_INTERVAL
PLS_INV
OPT_TXINV
OPT_RXINV
OPT_RXDIS
LCD_BLKMAP
LCD_SEG
LCD_Y
SLEEP
LCD_ONLY
V3P3SYS
TEST
MUX
DIO3,
DIO19/SEG39,
DIO20/SEG40,
DIO21/SEG41
(68 Pin Package Only)
V3P3D
TEMP
VBAT
VBAT
MOD
OPT_TXMOD
OPT_FDC
CE_LCTN