Datasheet

71M6521DE/DH/FE Data Sheet
Page: 42 of 107 Rev 3
Recommended
R
LED
DIO1
V3P3D
71M6521
V3P3SYS
DGND
VBAT
3.3V
Recommended
R
LED
DIO1
V3P3D
71M6521
V3P3SYS
DGND
VBAT
3.3V
Figure 8: Connecting an External Load to DIO Pins
DIO_R
Value
Resource Selected for DIO Pin
0 NONE
1 Reserved
2 T0 (counter0 clock)
3 T1 (counter1 clock)
4 High priority I/O interrupt (INT0 rising)
5 Low priority I/O interrupt (INT1 rising)
6 High priority I/O interrupt (INT0 falling)
7 Low priority I/O interrupt (INT1 falling)
Table 56: Selectable Controls using the DIO_DIR Bits
LCD Drivers
The device in the 68-pin QFN package contains 20 dedicated LCD segment drivers in addition to the 18 multi-use
pins described above. Thus, the device is capable of driving between 80 to 152 pixels of LCD display with 25% duty
cycle (or 60 to 114 pixels with 33% duty cycle). At eight pixels per digit, this corresponds to 10 to 19 digits.
The device in the 64-pin LQFP package contains 20 dedicated LCD segment drivers in addition to the 15 multi-use
pins described above. Thus, the device is capable of driving between 80 to 140 pixels of LCD display with 25% duty
cycle (or 60 to 105 pixels with 33% duty cycle). At eight pixels per digit, this corresponds to 10 to 17 digits.
The LCD drivers are grouped into four commons and up to 38 segment drivers (68-pin package), or 4 commons and
35 segment drivers (64-pin package). The LCD interface is flexible and can drive either digit segments or enunciator
symbols.
Segment drivers SEG18 and SEG19 can be configured to blink at either 0.5Hz or 1Hz. The blink rate is controlled by
LCD_Y. There can be up to four pixels/segments connected to each of these drivers. LCD_BLKMAP18[3:0] and
LCD_BLKMAP19[3:0] identify which pixels, if any, are to blink.
LCD interface memory is powered by the non-volatile supply. The bits of the LCD memory are
preserved in LCD and SLEEP modes, even if their pin is not configured as SEG. In this case, they can
be useful as general-purpose nonvolatile storage.
Battery Monitor
The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure Enable) bit
is set. While BME is set, an on-chip 45kΩ load resistor is applied to the battery and a scaled fraction of the battery
voltage is applied to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at
CE DRAM address 0x07. BME is ignored and assumed zero when system power is not available. See the Battery
Monitor section of the Electrical Specification section for details regarding the ADC LSB size and the conversion
accuracy.
Not recommended
71M6521
DIO1
R
V3P3D
LED
V3P3SYS
3.3V
DGND
VBAT
71M6521
DIO1
R
V3P3D
LED
V3P3SYS
3.3V
DGND
VBAT