Datasheet

71M6521DE/DH/FE Data Sheet
Page: 38 of 107 Rev 3
On-Chip Resources
Oscillator
The 71M6521DE/DH/FE oscillator drives a standard 32.768kHz watch crystal. These crystals are accurate and do not
require a high-current oscillator circuit. The 71M6521DE/DH/FE oscillator has been designed specifically to handle
these crystals and is compatible with their high impedance and limited power handling capability.
PLL and Internal Clocks
Timing for the device is derived from the 32.768kHz oscillator output. On-chip timing functions include the MPU
master clock, a real time clock (RTC), and the delta-sigma sample clock. In addition, the MPU has two general
counter/timers (see MPU section).
The ADC master clock, CKADC, is generated by an on-chip PLL. It multiplies the oscillator output frequency (CK32)
by 150.
The CE clock frequency is always CK32 * 150, or 4.9152MHz, where CK32 is the 32kHz clock. The MPU clock
frequency is determined by MPU_DIV and can be 4.9152MHz *2
-
MPU_DIV
Hz where MPU_DIV varies from 0 to 7
(MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152MHz down to 38.4kHz. The circuit also
generates a 2x MPU clock for use by the emulator. This clock is not generated when ECK_DIS is asserted by the
MPU.
The setting of MPU_DIV is maintained when the device transitions to BROWNOUT mode, but the time base in
BROWNOUT mode is 28,672Hz.
Real-Time Clock (RTC)
The RTC is driven directly by the crystal oscillator. It is powered by the net V2P5NV (battery-backed up supply). The
RTC consists of a counter chain and output registers. The counter chain consists of seconds, minutes, hours, day of
week, day of month, month, and year. The RTC is capable of processing leap years. Each counter has its own output
register. Whenever the MPU reads the seconds register, all other output registers are automatically updated. Since
the RTC clock is not coherent to the MPU clock, the MPU must read the seconds register until two consecutive reads
are the same (requires either 2 or 3 reads). At this point, all RTC output registers will have the correct time.
Regardless of the MPU clock speed, RTC reads require one wait state.
RTC time is set by writing to the RTC registers in I/O RAM. Each byte written to RTC must be delayed at least 3 RTC
cycles from any previous byte written to RTC. Hardware RTC write protection requires that a write to address 0x201F
occur before each RTC write. Writing to address 0x201F opens a hardware ‘enable gate’ that remains open until an
RTC write occurs and then closes. It is not necessary to disable interrupts between the write operation to 0x201F and
the RTC write because the ‘enable gate’ will remain open until the RTC write finally occurs
Two time correction bits, RTC_DEC_SEC and RTC_INC_SEC are provided to adjust the RTC time. A pulse on one of
these bits causes the time to be decremented or incremented by an additional second at the next update of the
RTC_SEC register. Thus, if the crystal temperature coefficient is known, the MPU firmware can integrate temperature
and correct the RTC time as necessary.
Temperature Sensor
The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference. The
MPU may request an alternate multiplexer frame containing the temperature sensor output by asserting MUX_ALT.
The primary use of the temperature data is to determine the magnitude of compensation required to offset the
thermal drift in the system (see section titled “Temperature Compensation”).