Datasheet

71M6521DE/DH/FE Data Sheet
Rev 3 Page: 37 of 107
Figure 6: Interrupt Structure
IE0
Individual
Interrupt
Flags
RI1
TI1
General
Interrupt
Flags
Internal/
External
Source
>=1
TF0
INT2
IE1
INT3
TF1
INT4
RI0
TI0
>=1
INT5
INT6
IRCON.1
I2FR
IRCON.2
I3FR
IRCON.3
IRCON.4
IRCON.5
IEN0.7
IP1.0/
IP0.0
IP1.1/
IP0.1
IP1.2/
IP0.2
IP1.3/
IP0.3
IP1.4/
IP0.4
IP1.5/
IP0.5
Interrupt
Control
Register
Priority
Assignment
Interrupt
Vector
Polling Sequence
Interrupt
Enable
Logic and
Polarity
Selection
DIO
UART1
(optical)
Timer 0
DIO
Timer 1
CE_BUSY
UART0
EEPROM/
I2C
XFER_BUSY
RTC_1S
IEN0.0
IEN2.0
IEN0.1
IEN1.1
IEN0.2
IEN1.2
IEN0.3
IEN1.3
IEN0.4
IEN1.4
IEN1.5
IE_XFER
IE_RTC
Flash Write
Collision
IE_FWCOL0
IE_FWCOL1
PLL OK
IE_PLLRISE
IE_PLLFALL