Datasheet

71M6521DE/DH/FE Data Sheet
Rev 3 Page: 33 of 107
Interrupt Request register (IRCON)
MSB LSB
EX6 IEX5 IEX4 IEX3 IEX2
Table 44: The IRCON Register
Bit Symbol Function
IRCON.7 -
IRCON.6 -
IRCON.5 IEX6
External interrupt 6 edge flag
IRCON.4 IEX5
External interrupt 5 edge flag
IRCON.3 IEX4
External interrupt 4 edge flag
IRCON.2 IEX3
External interrupt 3 edge flag
IRCON.1 IEX2
External interrupt 2 edge flag
IRCON.0 -
Table 45: The IRCON Bit Functions
Only TF0 and TF1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardware when the
service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service routine is
called).
External Interrupts
The 71M6521DE/DH/FE MPU allows seven external interrupts. These are connected as shown in Table 46. The
direction of interrupts 2 and 3 is programmable in the MPU. Interrupts 2 and 3 should be programmed for falling
sensitivity. The generic 8051 MPU literature states that interrupt 4 through 6 are defined as rising edge sensitive.
Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table
46.
External
Interrupt
Connection Polarity Flag Reset
0 Digital I/O High Priority
see DIO_Rx
automatic
1 Digital I/O Low Priority
see DIO_Rx
automatic
2 FWCOL0, FWCOL1 falling automatic
3 CE_BUSY falling automatic
4 PLL_OK (rising), PLL_OK (falling) rising automatic
5 EEPROM busy falling automatic
6 XFER_BUSY OR RTC_1SEC falling manual
Table 46: External MPU Interrupts
FWCOLx interrupts occur when the CE collides with a flash write attempt. See the flash write description for more
detail.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each
interrupt has its own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. Note that
XFER_BUSY, RTC_1SEC, FWCOL0, FWCOL1, PLLRISE, PLLFALL, have their own enable and flag bits in addition
to the interrupt 6, 4, and 2 enable and flag bits.
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other flags,
IE_XFER through IE_PB, are cleared by writing a zero to them. Since these bits are in a bit-addressable SFR byte,
common practice would be to clear them with a bit operation. This is to be avoided. The hardware implements bit
operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before the
write, its flag will be cleared unintentionally. The proper way to clear the flag bits is to write a byte mask consisting of
all ones except for a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.