Datasheet

71M6521DE/DH/FE Data Sheet
Rev 3 Page: 31 of 107
On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate
vector address, if the following conditions are met:
• No interrupt of equal or higher priority is already in progress.
• An instruction is currently being executed and is not completed.
• The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Special Function Registers for Interrupts:
Interrupt Enable 0 register (IE0)
MSB LSB
EAL WDT ES0 ET1 EX1 ET0 EX0
Table 35: The IEN0 Register
Bit Symbol Function
IEN0.7 EAL EAL=0 – disable all interrupts
IEN0.6 WDT
Not used for interrupt control
IEN0.5 -
IEN0.4 ES0 ES0=0 – disable serial channel 0 interrupt
IEN0.3 ET1 ET1=0 – disable timer 1 overflow interrupt
IEN0.2 EX1 EX1=0 – disable external interrupt 1
IEN0.1 ET0 ET0=0 – disable timer 0 overflow interrupt
IEN0.0 EX0 EX0=0 – disable external interrupt 0
Table 36: The IEN0 Bit Functions
Interrupt Enable 1 Register (IEN1)
MSB LSB
SWDT EX6 EX5 EX4 EX3 EX2
Table 37: The IEN1 Register
Bit Symbol Function
IEN1.7 -
IEN1.6 SWDT
Not used for interrupt control
IEN1.5 EX6 EX6=0 – disable external interrupt 6
IEN1.4 EX5 EX5=0 – disable external interrupt 5
IEN1.3 EX4 EX4=0 – disable external interrupt 4
IEN1.2 EX3 EX3=0 – disable external interrupt 3
IEN1.1 EX2 EX2=0 – disable external interrupt 2
IEN1.0 -
Table 38: The IEN1 Bit Functions