Datasheet

71M6521DE/DH/FE Data Sheet
Rev 3 Page: 25 of 107
MSB LSB
SM - SM21 REN1 TB81 RB81 TI1 RI1
Table 16: The S1CON register
Bit
Symbol
Function
S0CON.7 SM0
These two bits set the UART0 mode:
Mode
Description
SM0
SM1
0 N/A 0 0
1 8-bit UART 0 1
2 9-bit UART 1 0
3 9-bit UART 1 1
S0CON.6 SM1
S0CON.5 SM20
Enables the inter-processor communication feature.
S0CON.4 REN0
If set, enables serial reception. Cleared by software to disable reception.
S0CON.3 TB80
The 9
th
transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, depending
on the function it performs (parity check, multiprocessor communication etc.)
S0CON.2 RB80 In modes 2 and 3 it is the 9
th
data bit received. In Mode 1, if SM20 is 0, RB80 is the
stop bit. In mode 0 this bit is not used. Must be cleared by software
S0CON.1 TI0
Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be
cleared by software.
S0CON.0
RI0
Receive interrupt flag, set by hardware after completion of a serial reception. Must
be cleared by software
Table 17: The S0CON Bit Functions
Bit
Symbol
Function
S1CON.7 SM
Sets the baud rate for UART1
SM
Mode
Description
Baud Rate
0 A 9-bit UART variable
1 B 8-bit UART variable
S1CON.5 SM21
Enables the inter-processor communication feature.
S1CON.4 REN1
If set, enables serial reception. Cleared by software to disable reception.
S1CON.3 TB81
The 9
th
transmitted data bit in Mode A. Set or cleared by the MPU, depending on the
function it performs (parity check, multiprocessor communication etc.)
S1CON.2 RB81 In Modes A and B, it is the 9
th
data bit received. In Mode B, if SM21 is 0, RB81 is the
stop bit. Must be cleared by software
S1CON.1 TI1
Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be
cleared by software.
S1CON.0 RI1
Receive interrupt flag, set by hardware after completion of a serial reception. Must
be cleared by software
Table 18: The S1CON Bit Functions
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter
or timer operations.
In timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the
MPU clock signal.