Datasheet

71M6521DE/DH/FE Data Sheet
Page: 22 of 107 Rev 3
Register
SFR
Address
R/W Description
P0
0x80
R/W
Register for port 0 read and write operations (pins DIO4…DIO7)
DIR0
0xA2
R/W
Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is
an output.
P1
0x90
R/W
Register for port 1 read and write operations (pins DIO8…DIO11, DIO14-DIO15)
DIR1
0x91
R/W
Data direction register for port 1.
P2
0xA0
R/W
Register for port 2 read and write operations (pins DIO16…DIO17, DIO19…DIO21)
DIR2
0xA1
R/W
Data direction register for port 2.
Table 11: Port Registers
All DIO ports on the chip are bi-directional. Each of them consists of a Latch (SFR ‘P0’ to ‘P2’), an output driver, and
an input buffer, therefore the MPU can output or read data through any of these ports. Even if a DIO pin is configured
as an output, the state of the pin can still be read by the MPU, for example when counting pulses issued via DIO pins
that are under CE control.
The technique of reading the status of or generating interrupts based on DIO pins configured as outputs,
can be used to implement pulse counting.
Special Function Registers Specific to the 71M6521DE/DH/FE
Table 12 shows the location and description of the 71M6521DE/DH/FE-specific SFRs.
Register
Alternative
Name
SFR
Address
R/W Description
ERASE
FLSH_ERASE
0x94
W
This register is used to initiate either the Flash Mass Erase cycle or
the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle (default =
0x00).
0x55 – Initiate Flash Page Erase cycle. Must be preceded by a write
to FLSH_PGADR @ SFR 0xB7.
0xAA – Initiate Flash Mass Erase cycle. Must be preceded by a write
to FLSH_MEEN @ SFR 0xB2 and the debug port must be
enabled.
Any other pattern written to FLSH_ERASE will have no effect.
PGADDR
FLSH_PGADR
0xB7
R/W
Flash Page Erase Address register containing the flash memory
page address (page 0 thru 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-written for each new Page Erase cycle.
EEDATA
0x9E
R/W
I
2
C EEPROM interface data register
EECTRL
0x9F R/W
I
2
C EEPROM interface control register. If the MPU wishes to write a
byte of data to EEPROM, it places the data in EEDATA
and then
writes the ‘Transmit’ code to EECTRL. The write to EECTRL initiates
the transmit sequence. See the EEPROM Interface section for a
description of the command and status bits available for EECTRL.