Datasheet

71M6521DE/DH/FE Data Sheet
Page: 18 of 107 Rev 3
CKCON register Stretch Value Read signals width Write signal width
CKCON.2 CKCON.1 CKCON.0
memaddr memrd memaddr memwr
0 0 0 0 1 1 2 1
0
0
1
1
2
2
3
1
0 1 0 2 3 3 4 2
0 1 1 3 4 4 5 3
1 0 0 4 5 5 6 4
1 0 1 5 6 6 7 5
1 1 0 6 7 7 8 6
1 1 1 7 8 8 9 7
Table 5: Stretch Memory Cycle Width
There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the
external data RAM.
In the first type (MOVX A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight lower-ordered
bits of address. The eight high-ordered bits of address are specified with the USR2 SFR. This method allows the user
paged access (256 pages of 256 bytes each) to all ranges of the external data RAM. In the second type of MOVX
instruction (MOVX A,@DPTR), the data pointer generates a sixteen-bit address. This form is faster and more efficient
when accessing very large data arrays (up to 64 Kbytes), since no additional instructions are needed to set up the
eight high ordered bits of address.
It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two with direct
access and two with paged access to the entire 64KB of external memory range.
Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit
register that is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called
DPTR, the second data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data
pointer select bit is located at the LSB of the DPS register (DPS.0). DPTR is selected when DPS.0 = 0 and DPTR1 is
selected when DPS.0 = 1.
The user switches between pointers by toggling the LSB of the DPS register. All data pointer-related instructions use
the currently selected data pointer for any activity.
The second data pointer may not be supported by certain compilers.
Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal
data memory address is always 1 byte wide and can be accessed by either direct or indirect addressing. The Special
Function Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect
addressing accesses the upper 128 bytes of Internal RAM.