Datasheet

71M6521DE/DH/FE Data Sheet

Page: 14 of 107 Rev 3

The CE DRAM contains 128 32-bit words. The MPU can read and write the CE DRAM as the primary means of data

communication between the two processors.

Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE.

ADDRESS (HEX)

NAME

DESCRIPTION

Phase A current

Phase A voltage

Phase B current

Phase B voltage

Not used

TEMP

Temperature

VBAT

Battery Voltage

Table 2: CE DRAM Locations for ADC Results

The CE of the 71M6521DE/DH/FE is aided by support hardware that facilitates implementation of equations, pulse

counters, and accumulators. This support hardware is controlled through I/O RAM locations EQU (equation assist),

DIO_PV and DIO_PW (pulse count assist), and PRE_SAMPS and SUM_CYCLES (accumulation assist). PRE_SAMPS

and SUM_CYCLES support a dual level accumulation scheme where the first accumulator accumulates results from

PRE_SAMPS samples and the second accumulator accumulates up to SUM_CYCLES of the first accumulator results.

The integration time for each energy output is PRE_SAMPS * SUM_CYCLES/2520.6 (with MUX_DIV = 1). CE hardware

issues the XFER_BUSY interrupt when the accumulation is complete.

Meter Equations

Compute Engine (CE) firmware and hardware for residential meter configurations implement the equations listed in

Table 3. The register EQU (located in the I/O RAM) specifies the equation to be used based on the number of phases

used for metering.

EQU

0BDescription

Watt & VAR Formula

Element 0

Element 1

1 element, 2W 1φ with neutral current sense

and tamper detection (VA connected to VB)

VA IA VA IB

1 element, 3W 1φ

VA(IA-IB)/2

N/A

2 element, 4W 2φ

VA IA

VB IB

Table 3: Meter Equations.