Datasheet

71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 35 of 104
A Maxim Integrated Products Brand
Note 3: After a reset from an in-circuit emulator, the IE_XFER flag may not be cleared because the CE may continue to run.
The flags for the RTC_1SEC and the XFER_BUSY interrupts are located in the WDI SFR (address 0xE8).
Enable Bit
Description
Flag Bit
Description
EX0 Enable external interrupt 0 IE0 External interrupt 0 flag
EX1
Enable external interrupt 1
IE1
External interrupt 1 flag
EX2 Enable external interrupt 2 IEX2 External interrupt 2 flag
EX3
Enable external interrupt 3
IEX3
External interrupt 3 flag
EX4
Enable external interrupt 4
IEX4
External interrupt 4 flag
EX5 Enable external interrupt 5 IEX5 External interrupt 5 flag
EX6 Enable external interrupt 6 IEX6 External interrupt 6 flag
EX_XFER Enable XFER_BUSY interrupt IE_XFER XFER_BUSY interrupt flag
EX_RTC Enable RTC_1SEC interrupt IE_RTC RTC_1SEC interrupt flag
Table 44: Control Bits for External Interrupts
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 45:
Group
0 External interrupt 0 Serial channel 1 interrupt
1 Timer 0 interrupt - External interrupt 2
2 External interrupt 1 - External interrupt 3
3 Timer 1 interrupt - External interrupt 4
4 Serial channel 0 interrupt - External interrupt 5
5 - - External interrupt 6
Table 45: Priority Level Groups
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in
the special function register IP0 and one in IP1.
If requests of the same priority level are received simultaneously, an internal
polling sequence as per Table 49 determines which request is serviced first.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by
the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC,
which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 44),
and these interrupts must be cleared by the MPU software.
An overview of the interrupt structure is shown in Figure 7.