Datasheet

71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
NOVEMBER 2010
Page: 67 of 98 © 2005–2010 Teridian Semiconductor Corporation V2.7
A Maxim Integrated Products Brand
CE RAM Locations
CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by reading addresses 0 through 7, as listed below.
Address (HEX) Name Description
00
IA
Phase A current
01
VA
Phase A voltage
02
IB
Phase B current
03
-
Reserved
04
-
Reserved
05
-
Reserved
06
TEMP
Temperature
07
--
Reserved
CE Status Word
Since the CE_BUSY interrupt occurs at 2520.6Hz (or at 3276.8Hz when MUX_DIV = 2), it is desirable to minimize the
computation required in the interrupt handler of the MPU. The MPU can read CESTATUS at every CE_BUSY interrupt.
CE
Address
Name Description
0x51 CESTATUS See description of CE status word below
The CE Status Word is useful for generating early warnings to the MPU. It contains sag warnings for phase A, as well as F0,
the derived clock operating at the fundamental input frequency. CESTATUS provides information about the status of voltage
and input AC signal frequency, which are useful for generating an early power fail warning to initiate necessary data storage.
CESTATUS represents the status flags for the preceding CE code pass (CE_BUSY interrupt).
Note: The CE does not store sag alarms from one code pass to the next. CESTATUS is refreshed at every CE_BUSY
interrupt and remains valid for up to 100µs after the CE_BUSY interrupt occurs. Unsynchronized read operations of
CESTATUS will yield unreliable results.
The significance of the bits in CESTATUS is shown in the table below:
CESTATUS
[bit]
Name
Description
31-29
Not Used
These unused bits will always be zero.
28
F0
F0 is a square wave at the exact fundamental input frequency.
27
RESERVED
26
RESERVED
25 SAG_A
Normally zero. Becomes one when VA remains below SAG_THR for SAG_CNT
samples. Will not return to zero until VA rises above SAG_THR.
24-0
Not Used
These unused bits will always be zero.