Datasheet

71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
NOVEMBER 2010
Page: 44 of 98 © 2005–2010 Teridian Semiconductor Corporation V2.7
A Maxim Integrated Products Brand
Status
Bit
Name Read/
Write
Reset
State
Polarity Description
7 ERROR R 0 Positive 1 when an illegal command is received.
6 BUSY R 0 Positive 1 when serial data bus is busy.
5 RX_ACK R 1 Negative 0 indicates that the EEPROM sent an ACK bit.
4 TX_ACK R 1 Negative 0 indicates when an ACK bit has been sent to the EEPROM
3-0
CMD[3:0
]
W 0
Positive,
see CMD
Table
CMD Operation
0 No-op. Applying the no-op command will stop the I2C clock
(SCK, DIO4). Failure to issue the no-op command will keep
the SCK signal toggling.
2 Receive a byte from EEPROM and send ACK.
3 Transmit a byte to EEPROM.
5 Issue a ‘STOP’ sequence.
6 Receive the last byte from EEPROM and do not send ACK.
9 Issue a ‘START’ sequence.
Others No Operation, set the ERROR bit.
Table 57: EECTRL Status Bits
Internal Clocks and Clock Dividers
All internal clocks are based on the watch crystal frequency (CK32 = 32,768Hz) applied to the XIN and XOUT pins. The PLL
multiplies this frequency by 150 to 4.9152MHz. This frequency is supplied to the ADC, the FIR filter (CKFIR), the clock test
output pin (CKTEST), the CE DRAM and the clock generator. The clock generator provides two clocks, one for the MPU
(CKMPU) and one for the CE (CKCE).
The MPU clock frequency is determined by the I/O RAM register MPU_DIV (0x2004[2:0]) and can be CE*2
-MPU_DIV
Hz where
MPU_DIV varies from 0 to 7 (MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152MHz down to
38.4kHz.
The circuit also generates a 2x MPU clock for use by the emulator. This clock is not generated when the I/O RAM register
ECK_DIS (0x2005[5]) is asserted by the MPU.
Battery
The VBAT pin provides an input for an external battery that can be used to support the crystal oscillator, RTC, the WD_OVF bit
and XRAM in the absence of the main power supply. If the battery is not used, the VBAT pin should be connected to V3P3.
Internal Voltages (VBIAS, VBAT, V2P5)
The 71M6511 requires two supply voltages, V3P3A, for the analog section, and V3P3D, for the digital section. Both voltages
can be tied together outside the chip. The internal supply voltage V2P5 is generated by a regulator from the 3.3V supplies.
The battery voltage, VBAT, is required when crystal oscillator, RTC and XRAM are required to keep operating while V3P3D is
removed (battery mode). VBAT, usually supplied by an external battery, powers crystal oscillator, RTC and XRAM (and the
WD_OVF bit).
VBIAS (1.5V) is generated internally and used for the V1 comparator and for the reference of the temperature sensor.
Test Ports