Datasheet

71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
NOVEMBER 2010
Page: 21 of 98 © 2005–2010 Teridian Semiconductor Corporation V2.7
A Maxim Integrated Products Brand
FLSHCRL 0xB2
R/W
W
R/W
R
Bit 0 (FLSH_PWE): Program Write Enable:
0 – MOVX commands refer to XRAM Space, normal operation
(default).
1 – MOVX @DPTR,A moves A to Program Space (flash) @
DPTR.
This bit is automatically reset after each byte written to flash. Writes
to this bit are inhibited when interrupts are enabled.
Bit 1 (FLSH_MEEN): Mass Erase Enable:
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Bit 6 (SECURE):
Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and
may only be set. Attempts to write zero are ignored.
Bit 7 (PREBOOT):
Indicates that the preboot sequence is active.
WDI 0xE8
R/W
R/W
W
Only byte operations on the whole WDI register should be used
when writing. The byte must have all bits set except the bits that are
to be cleared.
The multi-purpose register WDI contains the following bits:
Bit 0 (IE_XFER): XFER Interrupt Flag:
This flag monitors the XFER_BUSY interrupt. It is set by hardware
and must be cleared by the interrupt handler
Bit 1 (IE_RTC): RTC Interrupt Flag:
This flag monitors the RTC_1SEC interrupt. It is set by hardware and
must be cleared by the interrupt handler
Bit 7 (WD_RST): WD Timer Reset:
The WDT is reset when a 1 is written to this bit.
INTBITS INT0…INT6 0xF8 R Interrupt inputs. The MPU may read these bits to see the input to
external interrupts INT0, INT1, up to INT6. These bits do not have
any memory and are primarily intended for debug use
Table 12: Special Function Registers
Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated
op-codes is contained in the 651X Software User’s Guide (SUG).
UART
The 71M6511 includes a UART (UART0) that can be programmed to communicate with a variety of AMR modules. A second
UART (UART1) is connected to the optical port, as described in the optical port description.
The UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at up to 38,400 bits/s
((with MPU clock = 1.2288MHz). The operation of each pin is as follows:
RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. The voltage applied
at RX must not exceed 3.6V.
TX: This pin is used to output the serial data. The bytes are output LSB first.
The 71M6511 has, several UART-related registers for the control and buffering of serial data.