User`s manual

Maxiflex T2 CPU User Manual 26 -© Omniflex
UMM124XBR04.pdf
5. The Data Interchange Table explained
5.1 DIT Table Layout
The Data Interchange Table (or DIT) in the T2 CPU’s provides access to up to 65,500 16-bit
data registers used for reading and writing all configuration and dynamic data in the CPU
and all of its I/O modules. Some of these registers reside in the CPU itself, while the
balance are accessed through the CPU as if they are registers in the CPU. These registers
form part of what is called the “extended” DIT.
The following table shows the address map of the DIT table for an entire MAXIFLEX system
as viewed from the T2 CPU. It is possible to access registers in each of the I/O modules
directly as if they are registers in the CPU using the addressing scheme shown below:
Maxiflex Master Rack
Maxiflex
Slot:
CPU
Dynamic
Data
Space
CPU
Config
Data
Space
I/O
Slot
1
I/O
Slot
2
I/O
Slot
3
I/O
Slot
4
I/O
Slot
5
I/O
Slot
6
I/O
Slot
7
DIT Start
Address:
0 64000 4000 8000 12000 16000 20000 24000 28000
DIT End
Address:
3999 65499 7999 11999 15999 19999 23999 27999 31999
Maxiflex Expansion Rack
Maxiflex
Slot:
I/O
Slot
8
I/O
Slot
9
I/O
Slot
10
I/O
Slot
11
I/O
Slot
12
I/O
Slot
13
I/O
Slot
14
I/O
Slot
15
DIT Start
Address:
32000 36000 40000 44000 48000 52000 56000 60000
DIT End
Address:
35999 39999 43999 47999 51999 55999 59999 63999
Table 5.1: DIT Address Map of the T2 CPU:
5.2 CPU Dynamic Data DIT Range
While the address range allocated to the CPU covers 4000 DIT Registers, the T2 CPU
currently supports only 3250 DIT registers. The remaining DIT registers from 3251 to 3999
are not available and therefore cannot be used for data storage.
These 3250 DIT registers reside in the memory of the CPU module itself and have the
fastest access time of all areas.
This area of the DIT is typically used to store dynamic, real time data.