Specifications

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in the CPU-controlled mode, the graphics
control bus links the graphics memory to
the
CPU main memory . The third set of controls
is used to specify address, read and write
sequences
to/from the STIC whIm the system
is in the CPU-controlled mode. Video output
codes from the STIC are applied to the color
oscillator/master clock generator for
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processing.
GRAPHICS MEMORY. The graphics memory
consists
of a graphics read only memory
(ROM) and two graphics random access
memories (RAMs). The two graphics RAMs
are connected to the graphics ROM by an
B-bit static address bus. Address and read
instructions are applied
to the graphics ROM
by the STIC.
Output from the graphics memory
is applied to the 14-bit secondary data bus.
COLOR OSCILLATOR/MASTER CLOCK
GENERATOR. The color oscillator/master
clock generator decodes the video
output
from the STIC and generates a clock signal for
system control. Oscillator frequency input
is obtained from a 7.159090 MHz crystal and
its associated trimmer capacitor.
The clock
generator provides a 3.579545 MHz clock
signal output. Video
information from the
STIC is applied to five inputs
to produce
composite sync.
color burst, line blanking,
screen blanking and video output.
The analog
outputs of the
color oscillator are combined
by four external precision resistors
to provide
a composite video signal
to the RF Modulator.
SYSTEM RANDOM ACCESS MEMORY (SYS·
TEM RAM).
The System RAM is a dual port
interface, 16-bit wide storage area
which
serves as the control decoder for CPU control
data. The System RAM receives data from the
CPU via a 16-bit bidirectional time-multiplexed
bus. The direction
of data travel is from the
CPU to the graphics
memory except during a
bus reversal condition.
This condition is
indicated when the CPU requests a read from
a graphics address on the 14-bit graphics
bus. A 3-bit control bus
from the CPU provides
StTODe signals to the System RAM . tor the
on-chip address latch and main
memory area.
PROGRAM READ ONLY MEMORY
(PRO·
GRAM ROM). The internal program area is
comprised
of an executive or system ROM
and a scratch pad memory.
The executive
-B-
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ROM contains system operating data. System
program data from the executive ROM is
transmitted along a 16-bit bidirectional data
bus. The program ROM contains program data
common to all external programs. Data from
the program ROM is transmitted along a 16-bit
bidirectional bus. A scratch pad
memory RAM
associated
with the program ROM is provided
for
computation of the program ROM data .
Interconnection of the program ROM and
the scratch pad
memory RAM is accomplished
through a 14-bit bidirectional data bus.
PROGRAMMABLE
SOUND GENERATOR.
The programmable sound generator (PSG.)
is a large scale integrated circuit (LSI) de-
signed
to produce a wide variety of sounds.
All control signals to the PSG are provided
by the CPU. Two B-bit general purpose I/O
ports are provided for user interface via the
hand controllers. The PSG
output is available
from three independenlly programmed analog
outputs . The outputs of the PSG is combined
on a single line, amplified and then applied
to the RF modulator to produce the audio
output at the television set.
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