User`s manual

Mainboard User’s Manual
20
AGP Master 1 WS
Write
This implements a single delay when writing to the
AGP Bus. By default, two-wait states are used by
the system, allowing for greater stability.
AGP Master 1 WS
Read
This implements a single delay when reading to
the AGP Bus. By default, two-wait states are used
by the system, allowing for greater stability.
Memory
Parity/ECC Check
Enable this item to allow BIOS to perform a parity
check to the POST memory tests. Select Enabled
only if the system DRAM supports parity checking.
Integrated Peripherals Page
This page sets up some parameters for peripheral devices
connected to the system.
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
Integrated Peripherals
Item Help
On-Chip IDE Channel0 Enabled
On-Chip IDE Channel1 Enabled
IDE Prefetch Mode Enabled
Primary Master PIO Auto
Primary Slave PIO Auto
Secondary Master PIO Auto
Secondary Slave PIO Auto
Primary Master UDMA Auto
Primary Slave UDMA Auto
Secondary Master UDMA Auto
Secondary Slave UDMA Auto
Init Display First PCI Slot
Onboard FDD Controller Enabled
Onboard Serial Port 1 3F8/IRQ4
Onboard IR Port Disabled
x UART 2 Mode Standard
x IR Function Duplex Half
x TX,RX inverting enable No, Yes
Onboard Parallel Port 378/IRQ7
Menu Level
↑
↑↑
↑ ↓
↓↓
↓ →
→→
→ ←
←←
←
: Move Enter : Select +/-/PU/PD:Value F10: Save ESC: Exit F1:General Help
F5:Previous Values F6:BestPref. Defaults F7:Optimized Defaults
On-Chip IDE
Channel 0,1
Use these items to enable or disable the PCI IDE
channels that are integrated on the mainboard.
IDE Prefetch Mode
The onboard IDE drive interfaces support IDE
prefetching, for faster drive access. If you install a
primary and secondary add-in IDE interface, set
this field to Disabled if the interface does not
support prefetching.