User`s manual

45
Advanced Chipset Features Option
This option displays a table of items that define critical timing
parameters of the mainboard components including the memory,
and the system logic. Generally, you should leave the items on
this page at their default values unless you are very familiar with
the technical specifications of your system hardware. If you
change the values incorrectly, you may introduce fatal errors or
recurring instability into your system.
CMOS Setup Utility – Copyright (C) 1984 – 2000 Award Software
Advanced Chipset Features
Item Help
Bank 0/1 DRAM Timing SDRAM 10ns
Bank 2/3 DRAM Timing SDRAM 10ns
Bank 4/5 DRAM Timing SDRAM 10ns
SDRAM Cycle Length 3
DRAM Clock Host CLK
Memory Hole Disabled
Read Around Write Disabled
Concurrent PCI/Host Disabled
System BIOS Cacheable Enabled
Video RAM Cacheable Enabled
AGP Aperture Size 64M
AGP-2X Mode Enabled
CPU to PCI Write Buffer Enabled
PCI Dynamic Bursting Enabled
PCI Master 0 WS Write Enabled
PCI Delay Transaction Enabled
PCI#2 Access #1 Retry Disabled
AGP Master 1 WS Write Enabled
AGP Master 1 WS Read Disabled
Menu Level
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: Move Enter : Select +/-/PU/PD:Value: F10: Save ESC: Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
Bank 0/1 2/3 4/5 DRAM Timing Default: 10 ns
The DRAM timing is controlled by the DRAM Timing Registers. The
timings programmed into this register are dependent on the system de-
sign. Slower rates may be required in certain system designs to support
loose layouts or slower memory.
SDRAM Cycle Length Default: 3
This item sets the timing and wait states for SDRAM memory. We re-
commend that you leave this item at the default value.