Specifications

58 Matrox Mura MPX Series – System Builder’s Guide
Note that in some cases it may be possible to capture analog RGB or DVI sources and transfer them
internally using a 16-bit YUV format. Doing so will reduce the amount of system bandwidth required
to transfer the input data, but it will also degrade the capture quality (since less data is being used to
represent each pixel). This option should be used only when necessary, and with sources, when the
quality of input capture can be sacrificed.
Regardless of the resolutions and formats of the various inputs, the available system bandwidth
shouldn’t be exceeded. Doing so will result in reduced system performance and/or instability.
PCI Express architecture overview
To understand how system architecture plays a role in the available bandwidth, a basic understanding
of the PCI Express architecture is helpful. This section provides a brief description of the PCI Express
architecture to provide enough background to understand the bandwidth calculations provided later
in this discussion.
PCI Express is a point-to-point serial transmission interface using high-speed differential signaling to
enable high-performance transfer of data within systems. The PCIe architecture is now in its third
generation, with each generation providing increased performance over its predecessor. The initial
PCIe specification defined a 2.5 Gb/s data transfer rate per lane, while second generation PCIe
increased the data rate to 5 Gb/s. The third generation of PCI Express (which is just becoming
available in systems at the time of this writing) has further increased the data transfer rate to 8 Gb/s
per lane of data. The table below summarizes the data transfer capabilities of the PCI Express
architecture based on generation and link width (the link width is the
size of the electrical connection
between two PCI Express devices).
The PCI Express specification also defines backward-compatibility between PCI Express devices.
That is, a device designed for Gen-3 PCI Express functions at Gen-2 speeds when connected to a
Gen-2 device, a Gen-2 device functions at Gen-1 speeds when connected to a Gen-1 device, and so on.
Link width
*
* The link width provides a measure of the data transfer capabilities of the link in a single direction. Since each PCI
Express lane contains both an upstream and a downstream link, the effective bandwidth is doubled. The numbers
in this table represent the maximum bandwidth available in each direction.
PCIe Gen-1 PCIe Gen-2 PCIe Gen-3
†‡
† While the serial data rate has only increased from 5 Gb/s to 8 Gb/s over second generation PCI Express, the
encoding of the serial data has changed, providing more efficient transfers and effectively doubling the data
transmission rate over Gen-2 PCI Express.
‡ Gen-3 PCI Express is currently in the introductory phase and isn’t yet available to end-users.
×1 250 MB/s 500 MB/s 1 GB/s
×4 1 GB/s 2 GB/s 4 GB/s
×8 2 GB/s 4 GB/s 8 GB/s
×16 4 GB/s 8 GB/s 16 GB/s