User`s guide

12 Execution Modes
• CPU h ardw are latency — Modern CPU s try to predict the next couple of
instructions, including branches, by the use of instruction pipelines. If
an interrupt occurs, the prediction fai ls and the pipeline has to be fully
reloaded. This process introduces an additional latency. Additionally,
because of interrupts, cache mis ses will occur.
• Interrupt handler entry and exit latency — Because an interrupt can stop
the currently executing task at any instruction and the interrupted task
has to resume p roper execution when the interrupting task completes
execution, its state has to be saved and restored accordingly. This includes
saving CPU data and address registers, including the stack pointer. In
the case that the interrupted task executed floating-point unit (FPU)
operations, the FPU stack has to be saved as well (108 bytes on a Pentium
CPU). This introduces additionally latency.
• Interrupt handler content latency — If a background task has been
executing for a longer time, say in a loop, its needed data w ill be available
in the cache. But as soon as an interrupt occurs and the interrupt service
handler is executed, the data needed in the interrupt handler might no
longer be in the cache, causing the CPU to reload it from slower RAM. This
introduces additional latency. Generally, an interrupt reduces the optimal
execution speed or introduces latency, because of its unpredictable nature.
The kernel in interrupt mode is close to optimal for executing code on a
PC-compatible system. However, interrupt mode introduces an overall
latency of a bout 8 µs. This is a significant amount of time when considering
that a 1 GHz C PU can execute thousands of instructions within 8 µs. This
time is equivalent to a Sim ulink model containing a hundred nontrivial
blocks. Additionally, because lower priority tasks have to be serviced as well,
a certain amount of headroom (at leas t 5%) is necessary, which can cause
additional cache misses and therefore nonoptimal execution speed.
12-4