User`s guide

Interrupt Mode

Interrupt M ode

Interrupt mode is the default real-timeexecutionmodefor the kernel. This

mode provides the greatest flexibility and is the mode you should choose

for any application that executes at the given base sample time without

overloading the CPU.

The scheduler ensure s real-time single-tasking and multitasking execution of

single-rate or multirate systems, including asynchronous events (interrupts).

Additionally, background tasks like host-target communication or updating

the target screen run in parallel with sample-time-based model tasks. This

allows you to interact with the target system while the target application

is executing in real time at high sample rates. This is made possible by an

interrupt-driven real-time scheduler that is responsible for executing the

various tasks according to their priority. The base sample time task can

interrupt any other task (larger sample time tasks or background tasks) and

execution of the interrupted tasks resumes as soon as the base sample time

task completes operation. This gives a quasi parallel execution scheme with

consideration to the priorities of th e tasks .

Latencies Introduced by Interrupt Mode

Compared to other modes, interrupt mode has more advantages. The

exception is the disadvantage of introducing a constant overhead, or latency,

thatreducestheminimalpossiblebasesampletimetoaconstantnumber.

The overhead is the sum of various factors related to the interrupt-driven

execution scheme and can be referred to a s overall interrupt latency. The

overall latency consists of the following parts, assuming that the currently

executing task is not executing a critical section and has therefore not

disabled any interrupt sources:

• Interrupt controller latency — In a PC-compatible system the interrupt

controller is not part of the x86-compatible CPU but part of the CPU chip

set. The controller is accessed over the I/O-port address space, which

introduces a read or w rite latency of about 1 µs for each 8–bit/16–bit

requesting an interrupt, and the controller has to be reset after the

interrupt has been serviced, a latency of about 5 µs is introduced to properly

handle the interrupt controller.

12-3