User`s guide

13 Using Model Verification Blocks
13-2
Model Verification Blocks and the Verification Manager
Simulink Model Verification library blocks monitor time-domain signals in your model
during simulation, according to the specifications that you assign to the blocks.
Note: To see a complete description of all Simulink model verification blocks, see the
“Model Verification” category in the Simulink documentation.
You set a verification block to assert when its signal leaves the limit or range that you
specify. During simulation, when the signal crosses the limit, the verification block can:
• Stop the simulation and bring immediate focus to that part of the model.
• Report the limit encounter with a logical signal output of its own. If the simulation
does not encounter the limit, the signal output is true. If the simulation encounters
the limit, the signal output is false.
The Verification Manager is a graphical interface in the Signal Builder dialog box. Using
this tool, you can manage all the Model Verification blocks in your model from a central
location.
If you have Simulink Control Design™ software, you can also monitor frequency-domain
characteristics such as:
• Gain and phase margins
• Peak magnitude
Note: For more information about the Simulink Control Design model verification blocks,
see “Model Verification” in the Simulink Control Design documentation.