User`s guide

11 Overview of Component Verification
11-8
Functions for Component Verification
The Simulink Verification and Validation software provides several functions that
facilitate the tasks associated with component verification.
Task Function
Simulate a Simulink model and log input signals to a
Model block in the model. If you modify the test cases in the
Signal Builder harness model, use this approach for logging
input signals to the harness model itself.
slvnvlogsignals
Create a harness model for a component, using logged input
signals if specified, or using the default signals.
A harness model contains four Simulink blocks as described
in “Prepare the Component for Verification” on page
12-4 in “Verify Generated Code for a Component”.
slvnvmakeharness
Merge test case data into a single data structure for batch
execution or harness generation.
slvnvmergedata
Merge test cases from several harness models into a single
harness model.
slvnvmergeharness
Extract an atomic subsystem or atomic subchart into a new
model.
slvnvextract
Simulate a model, executing the specified test cases to
record model coverage and outport values.
slvnvruntest
Invoke the Code Generation Verification (CGV) API, and
execute the specified test cases on the generated code for
the model.
slvnvruncgvtest
Component verification functions do not support the following Simulink software
features:
• Variable-step solvers for slvnvruntest
• Component interfaces that contain:
• Complex signals
• Variable-size signals
• Array of buses