User guide

System Generator for DSP Getting Started Guide www.xilinx.com 9
UG639 (v 14.3) October 16, 2012
FIR Filter Generation
FIR Filter Generation
System Generator includes a FIR Compiler block that targets the dedicated DSP48
hardware resources in the Virtex®-4 and Virtex-5 devices to create highly optimized
implementations that can run in excess of 500 Mhz. Configuration options allow
generation of direct, polyphase decimation, polyphase interpolation and oversampled
implementations. Standard MATLAB functions such as fir2 or the MathWorks FDAtool
can be used to create coefficients for the Xilinx FIR Compiler.