User guide

System Generator for DSP Getting Started Guide www.xilinx.com 75
UG639 (v 14.3) October 16, 2012
Additional Examples and Tutorials
Processor Examples
Shared Memory Examples
Topic Description
Tutorial Example -
Designing and
Simulating
MicroBlaze Processor
Systems
Demonstrates how to import a MicroBlaze processor created using
Xilinx Platform Studio into System Generator. A DSP48 block is
used as a co-processor to the MicroBlaze processor.
Designing PicoBlaze
Microcontroller
Applications
Demonstrates how to implement a PicoBlaze
™ program in System
Generator. The example programs the PicoBlaze to alter the output
frequency of a Direct Digital Synthesizer (DDS) during an interrupt.
Topic Description
Simulation across
various models
Illustrates shared memories communicating across Simulink
models.
Host PC Shared
Memory access
Developer studio project to communicate with a shared memory.
High Speed Video
Processing using
Hardware Co-
simulation
Discussion of a high-speed co-simulation buffering interface
followed by an example in which the interface is used to support
real-time processing of a video stream using a 5x5 filter kernel.
High speed I/O
Buffering
Illustrates high speed Shared Memory I/O Buffering Interface for
Hardware Co-simulation.
Generating Multiple
Cycle-True Islands for
Distinct Clocks
An example using two asynchronous clocks.
Shared Memory, To
FIFO, To Register, To
Register, From
Register
Demonstrates use of shared memories, FIFOs and registers to pass
information.
Frame-Based
Acceleration using
Hardware Co-
Simulation
Explains how to use frame or vector-based transfers to further
accelerate simulations using FPGA hardware co-simulation.
Tutorial Example -
Using System
Generator and SDK
to Co-Debug an
Embedded DSP
Design
Integrating a processor with custom logic such as those from
DSP designs is a fairly involved process. In this tutorial example,
you will learn how to perform hardware and software co-
debugging using System Generator and the Xilinx Software
Development Kit (SDK) together.