User guide

System Generator for DSP Getting Started Guide www.xilinx.com 73
UG639 (v 14.3) October 16, 2012
Additional Examples and Tutorials
ChipScope Examples
DSP Examples
Topic Description
Using ChipScope Pro
Analyzer for Real-
Time Hardware
Debugging
This tutorial demonstrates how to connect and use the Xilinx Debug
Tool called ChipScope
™ Pro within Xilinx System Generator for
DSP. The integration of ChipScope Pro in the System Generator flow
allows real-time debugging at system speed.
Topic Description
DSP48 Block Simple example demonstrating the use of the DSP48 block with the
Constant block used to provide the DSP48 instruction.
DSP48 Macro Block Simple example demonstrating how to use a DSP48 Macro block to
implement a Complex Multiplier.
DSP48 Block
(35-Bit Multiplier
using DSP48 and
Constant block)
This design demonstrates the use of the DSP48 and Constant block
in implementing 35 by 35-bit multipliers at different sample rates.
Three multipliers implementations are shown at 1, 2, and 4 clocks
per sample.
DSP48 Macro Block
(FIR filter using the
DSP48 Macro block as
a multiply accumulate
function)
This design demonstrates the use of the DSP48 Macro block in
implementing a 35 by 35 Multiplier.
DSP48 Block
FIR filter examples
using DSP48 block
This design demonstrates the use of the DSP48 and Constant block
in FIR filter implementation. The design includes sets of parallel,
semi-parallel and sequential FIR filter using Type 1 and Type 2
architectures. Each filter implements a 16-tap dsp48-based FIR
filters.
DSP48 Design
Techniques
(DSP48-based
dynamic shifter)
This design demonstrates the use of the DSP48 block in
implementing a 35-bit signed right shift using 2 DSP48s.
DSP48 Design
Techniques
(Synthesizable FIR
filter for Virtex®-4)
This design demonstrates how to use System Generator to
implement a synthesizable FIR filter which maps efficiently to the
Virtex®-4 architecture.
DSP48 Macro Block
(FIR filter using the
DSP48 Macro block as
a multiply accumulate
function)
This design demonstrates the use of the DSP48 Macro block when
implementing a sequential FIR filter.