User guide

68 www.xilinx.com System Generator for DSP Getting Started Guide
UG639 (v 14.3) October 16, 2012
Chapter 4: Getting Started
FIR Compiler Block
The Xilinx Fir Compiler block implements a high speed MAC based FIR filter. It accepts a stream of input data and
computes filtered output with a fixed delay, based on the filter configuration. The FIR Compiler supports
generation of resource shared or parallel FIR structures and polyphase decimation and interpolation structures.
Also supported is oversampling. Coefficients are specified using MATLAB commands.