User guide

System Generator for DSP Getting Started Guide www.xilinx.com 29
UG639 (v 14.3) October 16, 2012
Lesson 1 - Design Creation Basics
Generating the HDL Code
Once the design is completed, the hardware implementation files can be generated using the Generate button
available on the System Generator token properties editor. One option is to select HDL Netlist which allows the
FPGA implementation steps of RTL synthesis and place and route to be performed interactively using tool specific
user interfaces. Alternatively, you can select Bitstream as the Compilation target and System Generator will
automatically perform all implementation steps.
If the Create Testbench option is selected, then System Generator will save and write test vector files that are
extracted from the Simulink simulation and generate an HDL testbench and script files for ModelSim. This is an
optional step that simply verifies that the generated hardware is functionally equivalent to the Simulink simulation.
The script files must be used with ModelSim interactively.