User`s guide

Delay and Latency
3-89
The first column of ans is the Simulink time provided by the Digital Clock
block. You can see that the squared 2-norm of the first input,
[1 2 3 4]' ./ sum([1 2 3 4]'.^2)
appears in the first row of the output (at time t=0), the same time step that the
input was received by the block. This indicates that the Normalization block
has zero algorithmic delay.
Zero Algorithmic Delay and Algebraic Loops. When several blocks with zero
algorithmic delay are connected in a feedback loop, Simulink may report an
algebraic loop error and performance may generally suffer. You can prevent
algebraic loops by injecting at least one sample of delay into a feedback loop (for
example, by including an Integer Delay block with
Delay > 0). See the
Simulink documentation for more information about algebraic loops.
Basic Algorithmic Delay
A typical example of a block that does have algorithmic delay is the Variable
Integer Delay block.
The input to the
Delay port of the block specifies the number of sample periods
that should elapse before an input to the
In port is released to the output. This
value represents the block’s algorithmic delay. For example, if the input to the
Delay port is a constant 3, and the sample period at both ports is 1, then a
sample that arrives at the block’s
In port at time t=0 is released to the output
at time t=3.
Example: Basic Algorithmic Delay. Create the model shown below to observe the
operation of a block with basic delay.