User`s guide

3 Code Generation and the Build Process
3-30
Customizing and Creating Template Makefiles
To customize or create a new template makefile, you can copy an existing
template makefile to your local working directory and modify it.
The
make utility processes the model.mk makefile and generates a set of
commands based upon dependencies defined in
model.mk. For example, to
build a program called
test, make must link the object files. However, if the
object files don’t exist or are out of date,
make must compile the C code. After
make generates the set of commands needed to build or rebuild test, make
executes them.
Each version of
make differs slightly in its features and how rules are defined.
For example, consider a program called
test that gets created from two
sources,
file1.c and file2.c. Using most versions of make, the dependency
rules would be:
test: file1.o file2.o
cc −o test file1.o file2.o
file1.o: file1.c
cc −c file1.c
file2.o: file2.c
cc −c file2.c
In this example, we assumed a UNIX environment. In a PC environment the
file extensions and compile and link commands will be different. The first rule,
test: file1.o file2.o encountered by make will be built. In processing this
rule,
make sees that to build test, it needs to build file1.o and file2.o.To
build
file1.o, make processes the rule file1.o: file1.c and will compile
file1.c if file1.o doesn’t exist or is older than file1.c.
The format of Real-Time Workshop template makefiles follows the above
example. Our template makefiles use additional features of
make such as
macros and file-pattern-matching expressions. In most versions of
make,a
macro is defined via
MACRO_NAME = value
References to macros are made via $(MACRO_NAME).Whenmake sees this form
of expression, it substitutes
$(MACRO_NAME) with value.