User guide
Table Of Contents
- Return to Menu
- System Generator for DSP
- Table of Contents
- About This Guide
- Introduction
- Installation
- Release Information
- Getting Started
- Introduction
- Lesson 1 - Design Creation Basics
- The System Generator Design Flow
- The Xilinx DSP Blockset
- Defining the FPGA Boundary
- Adding the System Generator Token
- Creating the DSP Design
- Generating the HDL Code
- Model-Based Design using System Generator
- Creating Input Vectors using MATLAB
- Lesson 1 Summary
- Lab Exercise: Using Simulink
- Lab Exercise: Getting Started with System Generator
- Lesson 2 - Fixed Point and Bit Operations
- Lesson 3 - System Control
- Lesson 4 - Multi-Rate Systems
- Lesson 5 - Using Memories
- Lesson 6 - Designing Filters
- Additional Examples and Tutorials
- Index
96 www.xilinx.com System Generator for DSP Getting Started Guide
UG639 (v 12.2) July 23, 2010
Chapter 4: Getting Started
Timing Analysis Examples
Miscellaneous Examples
Topic Description
Tutorial Example:
Using the Timing
Analyzer
Explains how to use the System Generator Timing Analysis tool to
meet timing requirements of System Generator designs. Also
touches on techniques that may be used when a design does not
meet timing.
Topic Description
Importing a System
Generator Design into
a Bigger System
Discusses how to take the VHDL netlist from a System Generator
design and synthesize it in order to embed it into a larger design.
Also shows how VHDL created by System Generator can be
incorporated into simulation model of the overall system.
Configurable
Subsystems and
System Generator
Illustrates the use of Configurable Subsystems for Simulation and
Generation.
Integrator This example uses an integrator to illustrate error analysis
capability.
Block RAM-Based
State Machines
Demonstrates use of Mealy State Machine block from the reference
library.