User guide
Table Of Contents
- Return to Menu
- System Generator for DSP
- Table of Contents
- About This Guide
- Introduction
- Installation
- Release Information
- Getting Started
- Introduction
- Lesson 1 - Design Creation Basics
- The System Generator Design Flow
- The Xilinx DSP Blockset
- Defining the FPGA Boundary
- Adding the System Generator Token
- Creating the DSP Design
- Generating the HDL Code
- Model-Based Design using System Generator
- Creating Input Vectors using MATLAB
- Lesson 1 Summary
- Lab Exercise: Using Simulink
- Lab Exercise: Getting Started with System Generator
- Lesson 2 - Fixed Point and Bit Operations
- Lesson 3 - System Control
- Lesson 4 - Multi-Rate Systems
- Lesson 5 - Using Memories
- Lesson 6 - Designing Filters
- Additional Examples and Tutorials
- Index
80 www.xilinx.com System Generator for DSP Getting Started Guide
UG639 (v 12.2) July 23, 2010
Chapter 4: Getting Started
System Generator RAM Blocks
System Generator provides both a single- and dual-port RAM block. Depths up to 64K are supported. Both
Distributed RAM and Block RAM implementation options are available. System Generator calls the Xilinx memory
compiler to create an efficient memory structure in hardware for the given parameters, bit widths and depths. You
don’t need to be concerned with the hardware details of the specific Virtex® block or Distributed RAM structure.
Both the single- and dual-port RAM blocks support initialization. The signal connected to the address port of a
RAM must be unsigned with no fractional bits.