User guide
Table Of Contents
- Return to Menu
- System Generator for DSP
- Table of Contents
- About This Guide
- Introduction
- Installation
- Release Information
- Getting Started
- Introduction
- Lesson 1 - Design Creation Basics
- The System Generator Design Flow
- The Xilinx DSP Blockset
- Defining the FPGA Boundary
- Adding the System Generator Token
- Creating the DSP Design
- Generating the HDL Code
- Model-Based Design using System Generator
- Creating Input Vectors using MATLAB
- Lesson 1 Summary
- Lab Exercise: Using Simulink
- Lab Exercise: Getting Started with System Generator
- Lesson 2 - Fixed Point and Bit Operations
- Lesson 3 - System Control
- Lesson 4 - Multi-Rate Systems
- Lesson 5 - Using Memories
- Lesson 6 - Designing Filters
- Additional Examples and Tutorials
- Index
System Generator for DSP Getting Started Guide www.xilinx.com 77
UG639 (v 12.2) July 23, 2010
Lesson 4 - Multi-Rate Systems
Lab Exercise: Multi-Rate Systems
In this lab you will be exploring the effects of the rate changing blocks available in System
Generator. These blocks include Upsample, Downsample, Serial to Parallel and Parallel to
Serial.
The lab instructions and lab design are located in the System Generator software tree at the
following pathname:
<ISE_Design_Suite_tree>/sysgen/examples/getting_started_training/lab5/