User guide
Table Of Contents
- Return to Menu
- System Generator for DSP
- Table of Contents
- About This Guide
- Introduction
- Installation
- Release Information
- Getting Started
- Introduction
- Lesson 1 - Design Creation Basics
- The System Generator Design Flow
- The Xilinx DSP Blockset
- Defining the FPGA Boundary
- Adding the System Generator Token
- Creating the DSP Design
- Generating the HDL Code
- Model-Based Design using System Generator
- Creating Input Vectors using MATLAB
- Lesson 1 Summary
- Lab Exercise: Using Simulink
- Lab Exercise: Getting Started with System Generator
- Lesson 2 - Fixed Point and Bit Operations
- Lesson 3 - System Control
- Lesson 4 - Multi-Rate Systems
- Lesson 5 - Using Memories
- Lesson 6 - Designing Filters
- Additional Examples and Tutorials
- Index
System Generator for DSP Getting Started Guide www.xilinx.com 57
UG639 (v 12.2) July 23, 2010
Lesson 2 - Fixed Point and Bit Operations
The Reinterpret Block
The Reinterpret block forces the bits of a signal to a new type without regard for the numerical value or location of
the decimal point. This block does not change the number of bits of a signal but simply reinterprets the data type.
For example if the number 4 is represented as an unsigned [4 1] it is 1000. If this number is reinterpreted to be
unsigned [4 0], the 1000 is now 8.