User guide
Table Of Contents
- Return to Menu
- System Generator for DSP
- Table of Contents
- About This Guide
- Introduction
- Installation
- Release Information
- Getting Started
- Introduction
- Lesson 1 - Design Creation Basics
- The System Generator Design Flow
- The Xilinx DSP Blockset
- Defining the FPGA Boundary
- Adding the System Generator Token
- Creating the DSP Design
- Generating the HDL Code
- Model-Based Design using System Generator
- Creating Input Vectors using MATLAB
- Lesson 1 Summary
- Lab Exercise: Using Simulink
- Lab Exercise: Getting Started with System Generator
- Lesson 2 - Fixed Point and Bit Operations
- Lesson 3 - System Control
- Lesson 4 - Multi-Rate Systems
- Lesson 5 - Using Memories
- Lesson 6 - Designing Filters
- Additional Examples and Tutorials
- Index
System Generator for DSP Getting Started Guide www.xilinx.com 47
UG639 (v 12.2) July 23, 2010
Lesson 1 - Design Creation Basics
Adding the System Generator Token
Every System Generator diagram requires that at least one System Generator token be placed on the diagram. This
token is not connected to anything but serves to drive the FPGA implementation process. The property editor for
this token allows you to specify the target netlist, device, performance targets and system period. System Generator
will issue an error if this token is absent.