User guide
Table Of Contents
- Return to Menu
- System Generator for DSP
- Table of Contents
- About This Guide
- Introduction
- Installation
- Release Information
- Getting Started
- Introduction
- Lesson 1 - Design Creation Basics
- The System Generator Design Flow
- The Xilinx DSP Blockset
- Defining the FPGA Boundary
- Adding the System Generator Token
- Creating the DSP Design
- Generating the HDL Code
- Model-Based Design using System Generator
- Creating Input Vectors using MATLAB
- Lesson 1 Summary
- Lab Exercise: Using Simulink
- Lab Exercise: Getting Started with System Generator
- Lesson 2 - Fixed Point and Bit Operations
- Lesson 3 - System Control
- Lesson 4 - Multi-Rate Systems
- Lesson 5 - Using Memories
- Lesson 6 - Designing Filters
- Additional Examples and Tutorials
- Index
36 www.xilinx.com System Generator for DSP Getting Started Guide
UG639 (v 12.2) July 23, 2010
Chapter 3: Release Information
• Support has been added for all features in the underlying LogiCORE including the
puncturing feature.
Note:
This block supersedes the Convolutional Encoder v6_1 block. The Convolution Encoder
7.0 block presents the same customization and port interface that is available in the underlying
LogiCORE. The aclr input port has been removed.
Interleaver Deinterleaver 5.1
• Support added for Spartan-3A DSP
Note:
This block supersedes the Interleaver Deinterleaver v5_0 block. The Interleaver
Deinterleaver 5.1 block presents the same customization and port interface that is available in
the underlying LogiCORE.
Reed-Solomon Decoder 7.0
• Support added for Virtex-6 and Spartan-6
• Area optimization is now only selectable for the Virtex-5 family
• The maximum number of check symbols has been increased to 256 (was 128).
Note:
This block supersedes the Reed-Solomon Decoder 6.1 block. The Reed-Solomon
Decoder 7.0 block presents the same customization and port interface that is available in the
underlying LogiCORE. The aclr input port has been removed. The asynchronous reset input port
(reset) has been removed.
Reed-Solomon Encoder 7.0
• Support added for Virtex-6 and Spartan-6
Note:
This block supersedes the Reed-Solomon Decoder 6.1 block. The Reed-Solomon
Decoder 7.0 block presents the same customization and port interface that is available in the
underlying LogiCORE. The aclr input port has been removed. The asynchronous reset input port
(reset) has been removed.
Viterbi Decoder 7.0
• Support added for Virtex-6 and Spartan-6
• The aclr port has been removed because it is no longer supported by the underlying
LogiCORE
• Removed the speed option
Note:
This block supersedes the Viterbi Decoder v6_1 block. The Viterbi Decoder 7.0 block
presents the same customization and port interface that is available in the underlying LogiCORE.
The aclr input port and the speed option has been removed.
System Requirements and Recommendations
Hardware Recommendations
Recommendation Notes
2.00 GB of RAM
600 MB of hard disk space Minimum Requirement
Xilinx® Hardware Co-Simulation Platform Required for the Hardware Co-Simulation
Flow