User guide
Table Of Contents
- Return to Menu
- System Generator for DSP
- Table of Contents
- About This Guide
- Introduction
- Installation
- Release Information
- Getting Started
- Introduction
- Lesson 1 - Design Creation Basics
- The System Generator Design Flow
- The Xilinx DSP Blockset
- Defining the FPGA Boundary
- Adding the System Generator Token
- Creating the DSP Design
- Generating the HDL Code
- Model-Based Design using System Generator
- Creating Input Vectors using MATLAB
- Lesson 1 Summary
- Lab Exercise: Using Simulink
- Lab Exercise: Getting Started with System Generator
- Lesson 2 - Fixed Point and Bit Operations
- Lesson 3 - System Control
- Lesson 4 - Multi-Rate Systems
- Lesson 5 - Using Memories
- Lesson 6 - Designing Filters
- Additional Examples and Tutorials
- Index
System Generator for DSP Getting Started Guide www.xilinx.com 35
UG639 (v 12.2) July 23, 2010
Release Notes 11.4
Release Notes 11.4
System Generator Enhancements
New Device Support
• Spartan®-6 Low Power
• Spartan-6 XA
New Platform Support
System Generator now supports Ethernet Hardware Co-Simulation for the Virtex®-6
ML605 Platform
Xilinx Blockset Enhancements
New Blocks
DSP48 Macro 2.0
New block now available in System Generator with the following features:
• The primary change is that the DSP48 Macro block is now supported by an
underlying LogiCORE rather than being a System Generator basic block.
• Expanded instruction functionality coverage with the addition of 77 new opcode
instructions, bringing the opcode count from 72 to 149.
• Additional pipelining capability with the addition of Opmode, M Reg, and P Reg
Stages. The Macro supports three latency modes (Automatic, By Tier, and Expert).
Automatic and tiered are square latency models, the difference being that automatic
gives a fully pipelined model where as tiered allows for finer control.
• Reset & Enable Ports: DSP Macro v2.0 provides a global sclr (rst in System Generator)
and ce (en in System Generator) and does not provide access to individual enable and
reset ports of various registers in the XtremeDSP slice.
• Support for Pre-Adder in Virtex
®-6, Spartan®-6 and Spartan-3A DSP families,
including the Pre-Adder D Port.
• Support for various rounding capabilities.
• Now support up to 64 instructions, up from 8 in the previous System Generator block.
Existing Block Updates
The following blocks have been updated with the features mentioned below.
Complex Multiplier 3.1
• Support added for Spartan-6L and Spartan-6 XA
• Option added to configure latency.
Note:
This block supersedes the Complex Multiplier 3.0 block
Convolution Encoder 7.0
• Support added for Virtex-6 and Spartan-6