User guide
Table Of Contents
- Return to Menu
- System Generator for DSP
- Table of Contents
- About This Guide
- Introduction
- Installation
- Release Information
- Getting Started
- Introduction
- Lesson 1 - Design Creation Basics
- The System Generator Design Flow
- The Xilinx DSP Blockset
- Defining the FPGA Boundary
- Adding the System Generator Token
- Creating the DSP Design
- Generating the HDL Code
- Model-Based Design using System Generator
- Creating Input Vectors using MATLAB
- Lesson 1 Summary
- Lab Exercise: Using Simulink
- Lab Exercise: Getting Started with System Generator
- Lesson 2 - Fixed Point and Bit Operations
- Lesson 3 - System Control
- Lesson 4 - Multi-Rate Systems
- Lesson 5 - Using Memories
- Lesson 6 - Designing Filters
- Additional Examples and Tutorials
- Index
32 www.xilinx.com System Generator for DSP Getting Started Guide
UG639 (v 12.2) July 23, 2010
Chapter 3: Release Information
Convert
• An enable port has been added to the block interface.
DSP48 Macro 2.0
• Fixed the simulation of the DSP48 Macro when it is configured with zero latency i.e.
the block has a combinatorial path from input to output.
FIR Compiler 5.0
• Fixed the issue with incorrect output binary point for dout port when rounding is
being used for the output.
• Fixed the issue with incorrect settings being saved on the block if the coefficient vector
was not defined.
• Removed the restriction on non-availability of Symmetric Rounding Options for
Virtex-5 and Virtex-6 device family.
Interleaver Deinterleaver 6.0
• Support for Virtex-6, Virtex-6Q Virtex-6 Low Power, Spartan-6, Spartan-6Q, Spartan-6
Low Power
Note:
This block supersedes the Interleaver De-interleaver 5.1 block. The Interleaver
Deinterleaver 6.0 block presents the same customization and port interface that is available in
the underlying LogiCORE.
Fast Fourier Transform 7.0
• Removed support for Spartan-6 device family. Use Fast Fourier Transform 7.1 block
for Spartan-6 devices.
• This block has been superseded by Fast Fourier transform 7.1 block
Fast Fourier Transform 7.1
• Support added for Virtex-6 Q, Spartan-6, Spartan-6Q, Spartan-6 Low Power
Note:
This block supersedes the Fast Fourier Transform 7.0 block. The Fast Fourier Transform 7.1
block addresses the Spartan-6 9K Block RAM Simple Dual Port (SDP) Data Width Restriction as
described in Answer Record 34541
Reed Solomon Decoder 7.0
• Removed support for Spartan-6 device family. See Answer Record 34852 to add
support for Spartan-6 family for LogiCORE Reed Solomon Decoder
Reed Solomon Encoder 7.0
• Removed support for Spartan-6 device family. See Answer Record 34853 to add
support for Spartan-6 family for LogiCORE Reed Solomon Decoder