User guide
Table Of Contents
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- System Generator for DSP
- Table of Contents
- About This Guide
- Introduction
- Installation
- Release Information
- Getting Started
- Introduction
- Lesson 1 - Design Creation Basics
- The System Generator Design Flow
- The Xilinx DSP Blockset
- Defining the FPGA Boundary
- Adding the System Generator Token
- Creating the DSP Design
- Generating the HDL Code
- Model-Based Design using System Generator
- Creating Input Vectors using MATLAB
- Lesson 1 Summary
- Lab Exercise: Using Simulink
- Lab Exercise: Getting Started with System Generator
- Lesson 2 - Fixed Point and Bit Operations
- Lesson 3 - System Control
- Lesson 4 - Multi-Rate Systems
- Lesson 5 - Using Memories
- Lesson 6 - Designing Filters
- Additional Examples and Tutorials
- Index
System Generator for DSP Getting Started Guide www.xilinx.com 31
UG639 (v 12.2) July 23, 2010
Release Notes 12.1
System Generator & Software Development Kit (SDK) Co-Debug
(Beta Feature)
Xilinx ISE® Design Suite 12.1 includes a new beta feature that introduces key
improvements in the integration flow between System Generator, Xilinx Platform Studio
(XPS), and Software Development Kit (SDK). These improvements enable you to rapidly
import a MicroBlaze™ processor subsystem into System Generator and simulate the
processor through hardware co-simulation in order to debug a DSP circuit under
development. Co-debugging with System Generator and SDK is also enabled.
The following are some of benefits of using Co-Debug between System Generator and
SDK:
• Concurrent visibility of software and hardware for debug
♦ Set a breakpoint and debug while the MicroBlaze and hardware are stopped
♦ Signals to probe do not need to be chosen before the bit stream is generated
• Find a bug, modify the C code, recompile and update the bitstream in seconds.
♦ No need to rerun synthesis and the implementation flow when the software
changes
♦ The initial software program (ELF file) is automatically updated to the download
bitstream. You no longer need to manually click the Compile and update
bitstream button on the Hardware Co-Simulation block.
• Tight integration
♦ The SDK project is automatically set up with the correct hardware platform
♦ The required logic is automatically added to the design
For further information, refer to the topic Tutorial Example - Using System Generator and
SDK to Co-Debug an Embedded DSP Design
Note:
This feature is currently in "Beta" which means Xilinx is continuing to gather user feedback
with the goal of enhancing and improving the feature. Please email your feedback to
sdk_sysgen_codebug@xilinx.com.
Xilinx Blockset Enhancements
Existing Block Updates
The following blocks have been updated:
CIC Compiler 2.0
• Support for Virtex-6Q and Spartan-6Q
• Supports Automatic Update from CIC Compiler v1.1, v1.2 and v1.3
Note:
This block supersedes the CIC Compiler 1.3 block. The following timing changes will be
observed when updating from CIC Compiler 1.3. Following the application of a new rate change
value, using the RATE_WE and RATE signals, the core will update to the new rate on the next
input sample, for a single channel implementation, or the next input to the first channel, for
multiple channel implementations. The update will now cause the core internal state and output
signals to be reset.