User guide
Table Of Contents
- Return to Menu
- System Generator for DSP
- Table of Contents
- About This Guide
- Introduction
- Installation
- Release Information
- Getting Started
- Introduction
- Lesson 1 - Design Creation Basics
- The System Generator Design Flow
- The Xilinx DSP Blockset
- Defining the FPGA Boundary
- Adding the System Generator Token
- Creating the DSP Design
- Generating the HDL Code
- Model-Based Design using System Generator
- Creating Input Vectors using MATLAB
- Lesson 1 Summary
- Lab Exercise: Using Simulink
- Lab Exercise: Getting Started with System Generator
- Lesson 2 - Fixed Point and Bit Operations
- Lesson 3 - System Control
- Lesson 4 - Multi-Rate Systems
- Lesson 5 - Using Memories
- Lesson 6 - Designing Filters
- Additional Examples and Tutorials
- Index
30 www.xilinx.com System Generator for DSP Getting Started Guide
UG639 (v 12.2) July 23, 2010
Chapter 3: Release Information
Release Notes 12.1
System Generator Enhancements
New Device Support
• Virtex®-6 Q
• Spartan
®-6 Q
New Operating System Support
Native support for the following operating systems has been added:
• Windows XP 64-bit
• Windows VISTA 64-bit SP1
Hardware Co-Simulation Improvements
• System Generator now supports Ethernet Point-to-Point Hardware Co-Simulation for
the Spartan
®-6 FPGA SP601 and SP605 Platforms
• System Generator now provides support for more than one JTAG cable connected to
the computer. This provides:
♦ Support for multiple JTAG Hardware Co-Simulation blocks within one design
♦ Support for multiple boards connected to a single machine and the ability to use
any one of them. In the past, you had to physically disconnect all but one cable.
• System Generator now provides support for custom JTAG cables, like the cable used
to connect ChipScope.
• System Generator now auto detects the configuration cable between Platform USB
and Parallel Cable IV
For more detailed information, refer to the topic Configuring Co-Simulation Block
Parameters
Enhanced Integration with ChipScope
• A ChipScope block can now be included in a JTAG Hardware Co-Simulation design
• Repetitive-trigger data can now be imported with the xlLoadChipScopeData utility
function.
For more detailed information, refer to the topic xlLoadChipScopeData