User guide

Table Of Contents
System Generator for DSP Getting Started Guide www.xilinx.com 27
UG639 (v 12.2) July 23, 2010
Chapter 3
Release Information
Release Notes 12.2
System Generator Enhancements
System Generator 12.2 Performance Improvements
When opening a typical model in System Generator 12.2, you will see models open
about 2x faster the first time compared to System Generator 12.1. For additional
viewing of the model, you will typically see a 10x improvement compared to System
Generator 12.1.
When opening System Generator blocks such as the FFT, FIR Compiler, and DDS
Compiler in Release 12.2, you will see an average decrease in time of up to 30%
compared to System Generator 12.1.
When generating large designs for the first time, the netlisting time has been reduced
by an average of 20% compared to System Generator 12.1.
Hardware Co-Simulation Improvements
JTAG Co-simulation now supports a remote JTAG cable connection via the CSE
(ChipScope Engine) server (which is also being used with iMPACT software and
ChipScope Pro software). This allows you to run JTAG co-simulation over a JTAG cable
that is connected to a board in a remote location.
For more detailed information, refer to the topic Remote JTAG Cable Support in JTAG Co-
Simulation
MATLAB/Simulink Support
Production support for MATLAB®/Simulink 2010a.
Beta support for MATLAB/Simulink 2010b.
Xilinx Blockset Enhancements
Existing Block Updates
The following blocks have been updated:
Reed Solomon Decoder 7.1
Restored support for the Spartan-6 device family.