User`s guide

33
ADCTRL1 as seen in the Analog-to-Digital Converter Reference Guide
Bit(s) Name Description
15 Reserved Reads return a zero. Writes have no effect.
14 RESET ADC module software reset.
13−12 SUSMOD1−SUSMOD0 Emulation-suspend mode
11−8 ACQ_PS3 −ACQ_PS0 Acquisition window size.
7 CPS Core clock prescaler. Applies to HSPCLK.
6 CONT RUN Continuous run.
5 SEQ OVRD Sequencer override. Increases flexibility in continuous run.
4 SEQ CASC Cascaded sequencer operation.
3−0 Reserved Reads return zero. Writes have no effect.
Among the options for this register is a reset function – when activated it causes the entire
ADC module to reset, and then clears itself afterwards. This could be used to reboot after
break in the relay implementation discussed earlier.
As previously stated – this is just a small part of the available registers – please refer to the
Event Manager Reference Guide and the Analog-to-Digital Converter Reference Guide for
bit-specific actions and other registers.