User`s guide

14
The system clock frequency of 150MHz is divided by the high speed clock prescaler of 2, and
then divided by the timer control input clock prescaler, which is 128. The resulting frequency
is 0.586MHz.
Thus, one clock cycle is
586.0
1
MHz, which is 1.706µs. With 999 multiplications being
performed in the filter loop we get roughly
MFLOPS1.1
µs706.1540
999
≈
×
.
According to Texas Instruments, the DSP should be capable of 150 MMACS, Million
Multiply Accumulate Cycles per Second. This is a theoretical peak value, being the product of
the clock speed and the number of MACs, multiply-accumulate operations, that the DSP is
capable of executing per clock cycle.
The result of 1.1 MFLOPS seems a bit low, and the system should be able to perform a lot
better, whether this is due to interrupts or other “hidden” factors are unclear. Nonetheless
should 1+ MFLOPS be more than adequate for some power electronic applications which
depend on a 50 Hz signal.