User`s guide

Tar get Preferences
• Select Chip reset to generate a signal that resets the
processor (WDRST signal) and disable the watchdog
interrupt signal (W DIN T signal).
• Select
Raise WD Interrupt to generate a watchdog
interrupt signal (WDINT signal) and disable the reset
processor signal (WDRST signal). This signal can be used
to wake the device from an IDLE or STANDBY low-power
mode.
This parameter corresponds to bit 1 (WDENINT) of the
System Control and Status Register (SCSR).
GPIO[pin#]
Each pin selected for input offers three signal qualification types:
•
Sync to SYSCLKOUT — This setting is the default for all pins
at reset. Using this qualification type, the input signal is
synchronized to the system clock SYSCLKO U T. The following
figure shows the input signal measured on each tick of the
system clock, and the resulting output from the qualifier.
• Qualification using 3 samples — This setting requires
three cons ecutive cycles of the same value for the output value
to change . The following fi gure show s that, in the third cycle,
the GPIO v alue changes to
0, but the qualifier o utput is still 1
because it waits for three consecutive cycles of the same GPIO
value. The next three cycles all have a value of
0,andthe
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