User`s guide

Targ et Preferences

EQEP1I pin assignment

Select an option from the list—

GPIO23 or GPIO53.

Watchdog

When enabled, the watchdog rese ts the processor or generates

an interrupt if the software fails to reset the watchdog counter

within a speciﬁed interval. This feature enables the processor to

automatically recover from some fault conditio n s.

For more information, lo cate the Data Manual or System Control

and Interrupts Reference Guide foryourprocessorontheTexas

Instruments Web site.

Enable watchdog

Enable the watchdog time r modu l e .

This parameter corresponds to bit 6 (WDDIS) of

the W atchdog Control Register (WDCR) and bit 0

(WDOVERRIDE) of the System Control and Status Register

(SCSR).

Counter clock

Set the watchdog timer period relative to OSC CLK /512.

This parameter corres ponds to bits 2–0 (WD PS) of the

Watchdog Control Register (WDCR).

Timer period in seconds

This ﬁeld displays the timer period in seconds. This value

automatically updates when you change the Counter clock

parameter.

Time out event

Conﬁgure the watchdog to reset the processor or generate

an interrupt when the software fails to reset the watchdog

counter:

9-87