User`s guide

Targ et Preferences
Clock phase
Select
No_delay or Delay_half_cycle.
Clock polarity
Select
Rising_edge or Falling_edge.
Data bits
Length in bits from
1 to 16 of each transmitted or received
character. For example, if you select
8, the maximum data
that can be transmitted using SPI is
2
8-1
.Ifyousenddata
greater than this value, the buffer overflows.
Enable Loopback
Select this option to enable the loopback function for
self-test and diagnostic purposes only. When this function is
enable d, the Tx pin on a C28x DSP is internally conn ected
to its Rx pin and can transmit data from its o utput port to
its input port to check the integrity of the transmission.
Enable FIFO
Set true or false.
FIFO interrupt level (Rx)
Set level for receive FIFO interrupt. Select
0 through 16.
FIFO interrupt level (Tx)
Set level for transmit FIFO interrupt. Select
0 through 16.
FIFO transmit delay
Enter FIFO transmit delay (in processor clock cycles) to
pause betwe en data transmissions. Enter an integer.
Mode
Set to
Master or Slave.
CLK pin assignment
Assigns the SPI something (CLK) to a GPIO pin. Choices
are
None (default), GPI014,orGPI026.
SIMO pin assignment
Assigns the SPI something (SIMO) to a GPIO pin. Choices
are
None (default), GPI012,orGPI024.
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