User`s guide

Targ et Preferences
This parameter corresponds to bit 6 (AAS ) of the Interrupt
Enable Register (I2CIER).
Enable SCD interru pt
Enable stop condition detected interrupt.
When enabled, the I2C module generates an interrupt (SCD
bit = 1) when the CPU detects a stop condition on the I2C
bus.
When enabled, the I2C module clears the interrupt (SCD =
0) upon one of the following events:
• The CPU reads the I2CISRC while it indicates a stop
condition
• A reset of the I2C module
• Someone manually clears the interrupt
This parameter corresponds to bit 5 (SCD) of the Interrupt
Enable Register (I2CIER).
Enable ARDY interrupt
Enable register-access-ready interrupt enable bit.
When enabled, the I2C m odule generates an interrupt
(ARDY bit = 1) when the previous address, data, a nd
command values in th e I2C module registers have been used
and new values can be written to the I2C module registers.
This parameter corresponds to bit 2 (ARDY ) of the Interrupt
Enable Register (I2CIER).
Enable NACK interrupt
Enable no-acknowledgment interrupt enable bit.
When enabled, the I2C m odule generates an interrupt
(NACK bit = 1) when the module is a transmitter in master
or slave mode and it receives a NACK condition.
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