User`s guide

Targ et Preferences

Master clock H igh -time divider

When Mode is

Master, this divider determines the duration

of the high state on the serial clock pin (SCL) of the I2C-bus.

The high-time duration of the m aster clock = T mod x (ICCL

+d).

For more information about this value, consult the “Formula

for the Master Clock Period” section in the TMS320x280x

Inter-Integrated Circuit Module Reference Guide,Literature

Number: SPRU721A, available on the Texas Instruments

Web site.

This parameter corresponds to bits 15–0 (ICCH) of the C lock

High-Time Divider Register (I2CCLKH).

Enable loopback

When Mode is

Master, enable or disable digital loopback

mode. In digital loopback mode, I2CDXR transmits data

over an internal path to I2CDRR, w hich receives the data

after a conﬁgurable delay. The delay, measured in DSP

cycles, equals (I2C input clock frequency/module clock

frequency) x 8.

While Enable loopback is enabled, free data format

addressing is not supported.

This parameter corresponds to bit 6 (DLB) of the I2C Mode

Enable Tx Interrupt

This parameter corresponds to bit 5 (TXFFIENA) of the I2C

Transmit FIFO R egister (I2CFFTX).

Tx FIFO interrupt level

This parameter corresponds to bits 4–0 (TXFFIL4-0) of the

I2C Transmit FIFO R egister (I2CFFTX).

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