User`s guide

Targ et Preferences

You can set the following parameters for the AD C clock prescaler:

ACQ_PS

This value does not actually have a dire ct effect on the ADC

module’s core clock speed. It serves to determine the w idth

of the sampling or acquisition period. The higher the value,

the wider is the sampling period. The default value is

ADCLKPS

The HSPCLK speed is divided by this 4-bit v alue as the ﬁrst

step in deriving the ADC module’s core clock speed. The

default value is

CPS

After the HSPCLK speed is divided by the ADCLKPS value,

the result is further divided by 2 if the CPS parameter is

set to

1, which is the default.

External reference

By default, an internally generated bandgap voltage

reference is selected to supply the ADC logic. However,

depending on application requirements, the ADC logic may

be supplied by an external voltage reference. Choose

True

to use an external voltage reference.

Offset

The 280x ADC supports offset correction via a 9-bit value

that is added or subtracted before the results a re available

in the ADC result registers. Timing for results is not

affected. The default value is

eCAN_A

For m ore help on setting the timing parameters for the eCAN

modules, refer to Conﬁguring Timing Parameters for CA N Blocks.

You can set the following parameters for the eCAN module:

Baud rate prescaler

Value by which to scale the bit rate. Valid values are from

1 to 256.

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